Method for forming a current distribution structure

ABSTRACT

A method for forming an electrical structure. The electrical structure comprises an interconnect structure and a substrate. The substrate comprises an electrically conductive pad and a plurality of wire traces electrically connected to the electrically conductive pad. The electrically conductive pad is electrically and mechanically connected to the interconnect structure. The plurality of wire traces comprises a first wire trace, a second wire trace, a third wire trace, and a fourth wire trace. The first wire trace and second wire trace are each electrically connected to a first side of the electrically conductive pad. The third wire trace is electrically connected to a second side of the electrically conductive pad. The fourth wire trace is electrically connected to a third side of said first electrically conductive pad. The plurality of wire traces are configured to distribute a current.

This application is a divisional application claiming priority to Ser. No. 11/872,870, filed Oct. 16, 2007, now U.S. Pat. No. 7,911,803.

FIELD OF THE INVENTION

The present invention relates to forming an electrical structure for distributing a current signal.

BACKGROUND OF THE INVENTION

Structures formed on a substrate typically do not comprise the ability to route signals to various portions of the structures. Accordingly, there exists a need in the art to overcome at least one of the deficiencies and limitations described herein above.

SUMMARY OF THE INVENTION

The present invention provides an electrical structure comprising:

a first interconnect structure; and

a first substrate, wherein said first substrate comprises a first electrically conductive pad and a first plurality of wire traces electrically connected to said first electrically conductive pad, wherein said first electrically conductive pad is electrically and mechanically connected to said first interconnect structure, wherein said first plurality of wire traces comprises a first wire trace, a second wire trace, a third wire trace, and a fourth wire trace, wherein said first wire trace is electrically connected to a first side of said first electrically conductive pad, wherein said second wire trace is electrically connected to said first side of said first electrically conductive pad, wherein said third wire trace is electrically connected to a second side of said first electrically conductive pad, wherein said fourth wire trace is electrically connected to a third side of said first electrically conductive pad, wherein said first side of said first electrically conductive pad is connected to said second side of said first electrically conductive pad at a first non-zero degree angle, wherein said first side of said first electrically conductive pad is connected to said third side of said first electrically conductive pad at a second non-zero degree angle, wherein said first plurality of wire traces are configured to distribute a current traveling along said first plurality of wire traces such that said current enters said first electrically conductive pad in discrete locations in order to reduce electro migration of material comprised by said first interconnect structure, and wherein said first interconnect structure is configured to electrically connect said first electrically conductive pad to a second electrically conductive pad on a second substrate.

The present invention provides a method for forming an electrical structure comprising:

providing a first substrate;

forming a first electrically conductive pad on said first substrate;

forming a first plurality of wire traces on said first substrate, wherein said first plurality of wire traces are electrically connected to said first electrically conductive pad, wherein said first plurality of wire traces comprises a first wire trace, a second wire trace, a third wire trace, and a fourth wire trace, wherein said first wire trace is electrically connected to a first side of said first electrically conductive pad, wherein said second wire trace is electrically connected to said first side of said first electrically conductive pad, wherein said third wire trace is electrically connected to a second side of said first electrically conductive pad, wherein said fourth wire trace is electrically connected to a third side of said first electrically conductive pad, wherein said first side of said first electrically conductive pad is connected to said second side of said first electrically conductive pad at a first non-zero degree angle, wherein said first side of said first electrically conductive pad is connected to said third side of said first electrically conductive pad at a second non-zero degree angle, wherein said first plurality of wire traces are configured to distribute a current traveling along said first plurality of wire traces such that said current enters said first electrically conductive pad in discrete locations in order to reduce electro migration of material comprised by said first interconnect structure; and

forming a first interconnect structure electrically and mechanically connected to said first electrically conductive pad, wherein said first interconnect structure is configured to electrically connect said first electrically conductive pad to a second electrically conductive pad on a second substrate.

The present invention advantageously provides a simple structure and associated method for routing signals to various portions of structures.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates a top view of an electrical structure, in accordance with embodiments of the present invention.

FIG. 2 illustrates a cross sectional view of the electrical structure of FIG. 1, in accordance with embodiments of the present invention.

FIG. 3 depicts a first alternative to FIG. 1, in accordance with embodiments of the present invention

FIG. 4 depicts a second alternative to FIG. 1, in accordance with embodiments of the present invention.

FIG. 5 depicts a first alternative to FIG. 3 and FIG. 4, in accordance with embodiments of the present invention.

FIG. 6 depicts a third alternative to FIG. 1, in accordance with embodiments of the present invention

FIG. 7 depicts a first alternative to FIG. 6, in accordance with embodiments of the present invention

DETAILED DESCRIPTION OF THE INVENTION

FIG. 1 illustrates a top view of an electrical structure 4 a, in accordance with embodiments of the present invention. Electrical structure 4 a comprises an electrically conductive pad 12, a plurality of wire traces 14, a plurality of wire traces 16, an intermediate pad 10, a ball limiting metallurgy structure 15 (i.e., shown in FIG. 2), an interconnect structure 8, an insulator layer 19 (i.e., shown in FIG. 2), and a photosensitive polyimide (PSPI) layer 21 (i.e., shown in FIG. 2). Interconnect structure 8 may comprise a solder material. Solder material is defined herein as a metal alloy comprising a low melting point (i.e., about 100 degrees Celsius to about 340 degrees Celsius) that is used to join metallic surfaces together without melting the metallic surfaces. A solder material may include, inter alia, an alloy of tin such as SnCu, SnAgCu, SnPb, etc. Interconnect structure 8 may comprise a controlled collapse chip connector (C4) solderball. Alternatively, interconnect structure 8 may comprise a non-solder metallic material (i.e., does not comprise any solder material) such as, inter alia, copper, gold, nickel, etc. Intermediate pad 10 may comprise, inter alia, aluminum, etc. Electrical structure 4 a is formed on a substrate (i.e., substrate 7 illustrated in FIG. 2). Electrical structure 4 a electrically and mechanically connects components and/or circuits on substrate 7 to components and/or circuits on a second substrate (i.e., substrate 33 illustrated in FIG. 2). Wire traces 14 comprise a wire trace 14 a, a wire trace 14 b, a wire trace 14 c, a wire trace 14 d, and a wire trace 14 e. Wire trace is 14 a is electrically (and mechanically) connected to a side 12 b of electrically conductive pad 12. Wire trace is 14 b is electrically connected to a side 12 a of electrically conductive pad 12. The connection between wire trace 14 b and side 12 a is located adjacent to corner 18 a of electrically conductive pad 12. Wire trace is 14 d is electrically connected to side 12 a of electrically conductive pad 12. The connection between wire trace 14 d and side 12 a is located adjacent to corner 18 b of electrically conductive pad 12. Wire trace is 14 c is electrically connected to side 12 a of electrically conductive pad 12. The connection between wire trace 14 c and side 12 a is located on a portion of side 12 a located between the connection of wire trace 14 d and side 12 a and the connection of wire trace 14 b and side 12 a. Wire trace is 14 e is electrically connected to a side 12 c of electrically conductive pad 12. Wires traces 14 a, 14 b, 14 d, and 14 e each comprise a geometry that forms a plurality of angles (i.e., 90 degree angles). Wire traces 14 are formed in the aforementioned configuration so that a current signal (i.e., current signal originating from other components and/or circuits on substrate 7 or substrate 33) traveling along wire traces 14 in a direction 5 a is evenly distributed among wire traces 14 a . . . 14 e (or alternatively traveling from electrically conductive pad 12 to wire traces 14 in a direction 5 b). The current signal distributed among wire traces 14 a . . . 14 e enters electrically conductive pad 12 in discrete locations in order to reduce a current density of the current signal entering electrically conductive pad 12 and interconnect structure 8. A reduction in the current density entering interconnect structure 8 reduces an electro migration of material comprised by interconnect structure 8 (e.g., solder material, non-solder material, etc). Electro migration is defined herein as a migration or transport of material (e.g., material comprised by interconnect structure 8) caused by a gradual movement of ions (e.g., in the material comprised by interconnect structure 8) due to a momentum exchange between conducting electrons and diffusing metal atoms. Electro migration of material comprised by interconnect structure 8 causes portions of interconnect structure 8 to comprise a reduced density of material in the portions of interconnect structure 8.

Wire traces 16 comprise a wire trace 16 a, a wire trace 16 b, a wire trace 16 c, a wire trace 16 d, and a wire trace 16 e. Wire trace is 16 a is electrically (and mechanically) connected to side 12 b of electrically conductive pad 12. Wire trace is 16 b is electrically connected to side 12 d of electrically conductive pad 12. The connection between wire trace 16 b and side 12 d is located adjacent to corner 18 d of electrically conductive pad 12. Wire trace is 16 d is electrically connected to side 12 d of electrically conductive pad 12. The connection between wire trace 16 d and side 12 d is located adjacent to corner 18 c of electrically conductive pad 12. Wire trace is 14 c is electrically connected to side 12 d of electrically conductive pad 12. The connection between wire trace 16 c and side 12 d is located on a portion of side 12 d located between the connection of wire trace 16 d and side 12 d and the connection of wire trace 16 b and side 12 d. Wire trace is 16 e is electrically connected to side 12 c of electrically conductive pad 12. Wires traces 16 a, 16 b, 16 d, and 16 e each comprise a geometry that forms a plurality of angles (i.e., 90 degree angles). Wire traces 16 are formed in the aforementioned configuration so that a current signal (i.e., current signal originating from other components and/or circuits on substrate 7 or substrate 33) traveling along wire traces 16 in a direction 5 b is distributed among wire traces 16 a . . . 16 e (or alternatively traveling from electrically conductive pad 12 to wire traces 16 in a direction 5 a). The current signal distributed among wire traces 16 a . . . 16 e enters electrically conductive pad 12 in discrete locations in order to reduce a current density of the current signal entering electrically conductive pad 12 and interconnect structure 8. A reduction in the current density entering interconnect structure 8 reduces an electro migration of material comprised by interconnect structure 8 (e.g., solder material, non-solder material, etc).

FIG. 2 illustrates a cross sectional view of electrical structure 4 a of FIG. 1, in accordance with embodiments of the present invention. The cross sectional view of FIG. 2 is taken along line 2-2 of FIG. 1. The cross sectional view in FIG. 2 illustrates substrate 7, wire trace 14 c, electrically conductive pad 12, wire trace 16 c, intermediate pad 10, ball limiting metallurgy structure 15, interconnect structure 8, insulator layer 19, photosensitive polyimide (PSPI) layer 21, electrically conductive pad 23, and substrate 33. Electrically conductive pad 12 10 may be connected to wires or electrical components within substrate 7. Electrically conductive pad 23 may be connected to wires or electrical components within substrate 33. Substrate 7 may comprise, inter alia, a semiconductor device (e.g., an integrated circuit chip, a semiconductor wafer, etc), a chip carrier (organic or inorganic), a printed circuit board, etc. Substrate 33 may comprise, inter alia, a semiconductor device (e.g., an integrated circuit chip, a semiconductor wafer, etc), a chip carrier (organic or inorganic), a printed circuit board, etc. Insulator layer 19 may comprise any insulator material including, inter alia, silicon dioxide, silicon nitride, etc.

FIG. 3 depicts a first alternative to FIG. 1 illustrating a top view of an electrical structure 4 b, in accordance with embodiments of the present invention. Electrical structure 4 b of FIG. 3 comprises electrical structure 4 a of FIG. 1 and electrical structure 4 c similar to electrical structure 4 a. Electrical structure 4 c comprises an electrically conductive pad 15, a plurality of wire traces 24, a plurality of wire traces 28, an intermediate pad 10 a, a ball limiting metallurgy structure 15 (i.e., shown in FIG. 2), an interconnect structure 8 a, an insulator layer 19 (i.e., shown in FIG. 2), and a photosensitive polyimide (PSPI) layer 21 (i.e., shown in FIG. 2). Interconnect structure 8 a may comprise a solder material. Alternatively, interconnect structure 8 a may comprise a non-solder metallic material (i.e., does not comprise any solder material) such as, inter alia, copper, gold, nickel, etc. Intermediate pad 10 may comprise, inter alia, aluminum, etc. Electrical structure 4 c is formed on a substrate (i.e., substrate 7 illustrated in FIG. 2). Electrical structure 4 c electrically and mechanically connects components and/or circuits on substrate 7 to components and/or circuits on a second substrate (i.e., substrate 33 illustrated in FIG. 2). Wire traces 24 comprise a wire trace 24 a, a wire trace 24 b, a wire trace 24 c, a wire trace 24 d, and a wire trace 24 e. Wire trace is 24 a is electrically (and mechanically) connected to a side 15 b of electrically conductive pad 15. Wire trace is 24 b is electrically connected to a side 15 a of electrically conductive pad 15. The connection between wire trace 24 b and side 15 a is located adjacent to corner 19 a of electrically conductive pad 15. Wire trace is 24 d is electrically connected to side 15 a of electrically conductive pad 15. The connection between wire trace 24 d and side 15 a is located adjacent to corner 198 b of electrically conductive pad 15. Wire trace is 24 c is electrically connected to side 15 a of electrically conductive pad 15. The connection between wire trace 24 c and side 15 a is located on a portion of side 15 a located between the connection of wire trace 24 d and side 15 a and the connection of wire trace 24 b and side 15 a. Wire trace is 24 e is electrically connected to a side 15 c of electrically conductive pad 15. Wires traces 15 a, 15 b, 15 d, and 15 e each comprise a geometry that forms a plurality of angles (i.e., 90 degree angles). Wire traces 24 are formed in the aforementioned configuration so that a current signal (i.e., current signal originating from other components and/or circuits on substrate 7 or substrate 33 or from electrical structure 4 a) traveling along wire traces 24 in a direction 5 a is evenly distributed among wire traces 24 a . . . 24 e (or alternatively traveling from electrically conductive pad 15 to wire traces 24 in a direction 5 b). The current signal distributed among wire traces 24 a . . . 24 e enters electrically conductive pad 15 in discrete locations in order to reduce a current density of the current signal entering electrically conductive pad 15 and interconnect structure 8 a. A reduction in the current density entering interconnect structure 8 a reduces an electro migration of material comprised by interconnect structure 8 a (e.g., solder material, non-solder material, etc). Electro migration of material comprised by interconnect structure 8 a causes portions of interconnect structure 8 a to comprise a reduced density of material in the portions of interconnect structure 8 a.

Wire traces 28 comprise a wire trace 28 a, a wire trace 28 b, a wire trace 28 c, a wire trace 28 d, and a wire trace 28 e. Wire trace is 28 a is electrically (and mechanically) connected to side 28 b of electrically conductive pad 15. Wire trace is 28 b is electrically connected to side 15 d of electrically conductive pad 15. The connection between wire trace 28 b and side 15 d is located adjacent to corner 19 d of electrically conductive pad 12. Wire trace is 16 d is electrically connected to side 12 d of electrically conductive pad 15. The connection between wire trace 28 d and side 15 d is located adjacent to corner 19 c of electrically conductive pad 15. Wire trace is 14 c is electrically connected to side 12 d of electrically conductive pad 12. The connection between wire trace 28 c and side 15 d is located on a portion of side 15 d located between the connection of wire trace 28 d and side 15 d and the connection of wire trace 28 b and side 15 d. Wire trace is 28 e is electrically connected to side 15 c of electrically conductive pad 15. Wires traces 28 a, 28 b, 28 d, and 28 e each comprise a geometry that forms a plurality of angles (i.e., 90 degree angles). Wire traces 28 are formed in the aforementioned configuration so that a current signal (i.e., current signal originating from other components and/or circuits on substrate 7 or substrate 33) traveling along wire traces 16 in a direction 5 b is distributed among wire traces 28 a . . . 28 e (or alternatively traveling from electrically conductive pad 15 to wire traces 28 in a direction 5 a). The current signal distributed among wire traces 28 a . . . 28 e enters electrically conductive pad 15 in discrete locations in order to reduce a current density of the current signal entering electrically conductive pad 15 and interconnect structure 8 a. A reduction in the current density entering interconnect structure 8 a reduces an electro migration of material comprised by interconnect structure 8 a (e.g., solder material, non-solder material, etc).

Wire traces 16 of electrical structure 4 a are electrically and mechanically connected to wire traces 24 of electrical structure 4 c thereby electrically and mechanically connecting electrical structure 4 a to electrical structure 4 c in order to form electrical structure 4 b.

FIG. 4 depicts a second alternative to FIG. 1 illustrating a top view of an electrical structure 4 d, in accordance with embodiments of the present invention. Electrical structure 4 d of FIG. 4 comprises electrical structure 4 a of FIG. 1 electrically and mechanically connected to a single wire trace 17. Electrical structure 4 d is formed on a substrate (i.e., substrate 7 illustrated in FIG. 2). Electrical structure 4 d electrically and mechanically connects components and/or circuits on substrate 7 to components and/or circuits on a second substrate (i.e., substrate 33 illustrated in FIG. 2). Single wire trace 17 may be connected to electrical circuits or electrical components on substrate 7.

FIG. 5 depicts a first alternative to FIG. 3 and FIG. 4 illustrating a top view of an electrical structure 4 e, in accordance with embodiments of the present invention. Electrical structure 4 e of FIG. 5 comprises electrical structure 4 d of FIG. 4 electrically and mechanically connected to electrical structure 4 c of FIG. 3 via single wire trace 17. Electrical structure 4 e is formed on a substrate (i.e., substrate 7 illustrated in FIG. 2).

FIG. 6 depicts a third alternative to FIG. 1 illustrating a top view of an electrical structure 4 f, in accordance with embodiments of the present invention. In contrast with electrical structure 4 a of FIG. 1, electrical structure 4 f of FIG. 6 comprises plurality of wire traces 31 and plurality of wire traces 34. Wire traces 31 comprises wire traces 31 a . . . 31 e. Wire traces 31 a, 31 b, 31 d, and 31 e each comprise a curved wire section mechanically and electrically connected to electrically conductive pad 12. Wire traces 34 comprise wire traces 34 a . . . 34 e. Wire traces 34 a, 34 b, 34 d, and 34 e each comprise a curved wire section mechanically and electrically connected to electrically conductive pad 12.

FIG. 7 depicts a first alternative to FIG. 6 illustrating a top view of an electrical structure 4 g, in accordance with embodiments of the present invention. In contrast with electrical structure 4 f of FIG. 6, electrical structure 4 g of FIG. 7 comprises plurality of wire traces 35 and plurality of wire traces 38. Wire traces 35 comprises wire traces 35 a . . . 35 e. Wire traces 35 a, 35 b, 35 d, and 35 e each comprise an angular wire section (i.e., comprising at least one internal angle within a traversing path of each of wire traces 35 a, 35 b, 35 d, and 35 e and may comprise a non-ninety degree angle) mechanically and electrically connected to electrically conductive pad 12. Wire traces 38 comprise wire traces 38 a . . . 38 e. Wire traces 38 a, 38 b, 38 d, and 38 e each comprise an angular wire section (i.e., comprising at least one internal angle within a traversing path of each of wire traces 38 a, 38 b, 38 d, and 38 e and may comprise a non-ninety degree angle) mechanically and electrically connected to electrically conductive pad 12.

While embodiments of the present invention have been described herein for purposes of illustration, many modifications and changes will become apparent to those skilled in the art. Accordingly, the appended claims are intended to encompass all such modifications and changes as fall within the true spirit and scope of this invention. 

What is claimed is:
 1. A method for forming an electrical structure comprising: providing a first substrate; forming a first electrically conductive pad on said first substrate; forming a first plurality of wire traces on said first substrate, wherein said first plurality of wire traces are electrically connected to said first electrically conductive pad, wherein said first plurality of wire traces comprises a first wire trace, a second wire trace, a third wire trace, and a fourth wire trace, wherein said first wire trace is electrically connected to said first electrically conductive pad, wherein said first wire trace comprises an independent wire trace that is mechanically connected to a first side of said first electrically conductive pad, wherein said second wire trace is electrically connected to said first electrically conductive pad, wherein said second wire trace comprises an independent wire trace that is mechanically connected to said first side of said first electrically conductive pad, wherein said third wire trace is electrically connected to said first electrically conductive pad, wherein said third wire trace comprises an independent wire trace that is mechanically connected to a second side of said first electrically conductive pad, wherein said fourth wire trace is electrically connected to said first electrically conductive pad, wherein said fourth wire trace comprises an independent wire trace that is mechanically connected to a third side of said first electrically conductive pad, wherein said first side of said first electrically conductive pad differs from said second side of said first electrically conductive pad and said third side of said first electrically conductive pad, wherein said second side of said first electrically conductive pad differs from said third side of said first electrically conductive pad, wherein said first side of said first electrically conductive pad is connected to said second side of said first electrically conductive pad at a first non-zero degree angle, wherein said first side of said first electrically conductive pad is connected to said third side of said first electrically conductive pad at a second non-zero degree angle; forming an insulator layer mechanically connected said first electrically conductive pad; forming an intermediate conductive pad mechanically and electrically connected to said first electrically conductive pad and said insulator layer; forming a photosensitive polyimide layer mechanically connected said intermediate conductive pad and said insulator layer forming a metallurgy structure mechanically and electrically connected to said intermediate conductive pad, wherein said photosensitive polyimide layer is formed between and mechanically connected to a portion of said metallurgy structure and a portion of said intermediate conductive pad, wherein a portion of said insulator layer is formed between said intermediate conductive pad and said first electrically conductive pad, and wherein said intermediate conductive pad is formed between and electrically and mechanically connected to said first electrically conductive pad and said metallurgy structure; and forming a first interconnect structure electrically and mechanically connected to said metallurgy structure, wherein said first plurality of wire traces are configured to distribute a current traveling along said first plurality of wire traces such that said current enters said first electrically conductive pad in discrete locations in order to reduce electro migration of material comprised by said first interconnect structure, and wherein said first interconnect structure is configured to electrically connect said first electrically conductive pad to a second electrically conductive pad on a second substrate.
 2. The method of claim 1, wherein second side of said first electrically conductive pad is perpendicular to said first side of said first electrically conductive pad, and wherein said third side of said first electrically conductive pad is perpendicular to said first side of said first electrically conductive pad.
 3. The method of claim 2, wherein said first wire trace is electrically connected to a first portion of said first side of said first electrically conductive pad, wherein said first portion is adjacent to a first corner formed from said first side of said first electrically conductive pad and said second side of said first electrically conductive pad, wherein said second wire trace is electrically connected to a second portion of said first side of said first electrically conductive pad, and wherein said second portion is adjacent to a second corner formed from said first side of said first electrically conductive pad and said third side of said first electrically conductive pad.
 4. The method of claim 1, further comprising: forming a second plurality of wire traces on said first substrate, wherein said second plurality of wire traces are electrically connected to said first electrically conductive pad, wherein said second plurality of wire traces comprises a fifth wire trace, a sixth wire trace, a seventh wire trace, and an eighth wire trace, wherein said fifth wire trace is electrically connected to a fourth side of said first electrically conductive pad, wherein said sixth wire trace is electrically connected to said fourth side of said first electrically conductive pad, wherein said seventh wire trace is electrically connected to said second side of said first electrically conductive pad, wherein said eighth wire trace is electrically connected to said third side of said first electrically conductive pad, wherein said fourth side of said first electrically conductive pad is connected to said second side of said first electrically conductive pad at a third non-zero degree angle, and wherein said fourth side of said first electrically conductive pad is connected to said third side of said first electrically conductive pad at a fourth non-zero degree angle.
 5. The method of claim 1, further comprising: forming a single wire trace on said first substrate, wherein said single wire trace is electrically connected to said first plurality of wire traces.
 6. The method of claim 5, further comprising: forming a third electrically conductive pad on said first substrate; forming a second plurality of wire traces on said first substrate, wherein said second plurality of wire traces are electrically connected to said third electrically conductive pad, wherein said single wire trace is electrically connected to said second plurality of wire traces, wherein said second plurality of wire traces comprises a fifth wire trace, a sixth wire trace, a seventh wire trace, and an eighth wire trace, wherein said fifth wire trace is electrically connected to a first side of said third electrically conductive pad, wherein said sixth wire trace is electrically connected to said first side of said third electrically conductive pad, wherein said seventh wire trace is electrically connected to a second side of said third electrically conductive pad, wherein said eighth wire trace is electrically connected to a third side of said third electrically conductive pad, wherein said first side of said third electrically conductive pad is connected to said second side of said third electrically conductive pad at a third non-zero degree angle, and wherein said first side of said third electrically conductive pad is connected to said third side of said third electrically conductive pad at a fourth non-zero degree angle; and forming a second interconnect structure electrically and mechanically connected to said third electrically conductive pad, wherein said second interconnect structure is configured to electrically connect said third electrically conductive pad to a fourth electrically conductive pad on said second substrate.
 7. The method of claim 1, wherein said first wire trace comprises: a first section that is perpendicular to said first side, a second section that is parallel to said first side, and a third section is perpendicular to said first side, wherein said second wire trace comprises: a first section that is perpendicular to said first side, a second section that is parallel to said first side, and a third section that is perpendicular to said first side, wherein said third wire trace comprises: a first section that is perpendicular to said first side, a second section that is parallel to said first side, a third section that is parallel to said second side, and a fourth section that is perpendicular to said second side, and wherein said fourth wire trace comprises: a first section that is perpendicular to said first side, a second section that is parallel to said first side, a third section that is parallel to said second side, and a fourth section that is perpendicular to said second side.
 8. The method of claim 1, wherein said first wire trace comprises a first curved section electrically connected to said first side of said first electrically conductive pad, wherein said second wire trace comprises a second curved section electrically connected to said first side of said first electrically conductive pad, wherein said third wire trace comprises a third curved section electrically connected to said second side of said first electrically conductive pad, and wherein said fourth wire trace comprises a fourth curved section electrically connected to said third side of said first electrically conductive pad.
 9. The method of claim 1, wherein said first interconnect structure comprises a solder material.
 10. The method of claim 9, wherein said solder interconnect structure comprises a controlled collapse chip connector (C4) solderball.
 11. The method of claim 1, wherein said first interconnect structure comprises a non-solder interconnect structure that does not comprise any solder material.
 12. The method of claim 1, wherein a first portion of said insulator layer is formed between said photosensitive polyimide layer and said first electrically conductive pad.
 13. The method of claim 1, wherein a portion of said photosensitive polyimide layer is formed between said metallurgy structure and said insulator layer.
 14. The method of claim 1, wherein said photosensitive polyimide layer is mechanically connected to a first vertical surface and a second vertical surface of said intermediate conductive pad, and wherein said photosensitive polyimide layer is mechanically connected to a first horizontal surface and a second horizontal surface of said intermediate conductive pad.
 15. The method of claim 14, wherein said photosensitive polyimide layer is mechanically connected to a first horizontal surface of said metallurgy structure and a first angular surface of said metallurgy structure. 